Combinational and Sequential Logic Design

Task 1 :

Design a combinational circuit which produces a logic 1 output when the majority of bits of a four bit number are at logic 0. 

Minimise the design using either boolean algebra of Karnaugh maps and design the minimised circuit using a combination of AND, OR and NOT gates. 

Show how the circuit can be redsigned using NAND only logic

Simulate both circuits using Proteus and show graphically that the output meets the design requirements for both circuits.

Marks will be awarded as follows :

Theoretical design of the circuit and circuit diagram using AND, OR and NOT gates (5 Marks)

Conversion to NAND only logic (2 Marks)

Schematics for AND, OR NOT implementation (4 Marks) 

Schematics for NAND only implementation (4 Marks) 

Graphical output for AND, OR NOT implementation (2 Marks)

Graphical output for NAND only implementation (2 Marks)

Task 2 :

Based on the methodology discussed in the lecture notes, design and simulate a single bit full adder circuit.

Extend your design to a 4 bit full adder and test its operations.

Marks will be awarded as follows :

Theoretical design of full adder (5 Marks)

Schematic of Full Adder using Proteus ( 4 Marks)

Simulation graphical output of full adder (4 Marks)
Schematic Design of 4 bit Ripple adder using Proteus (10 Marks)

Simulation graphs to show that the circuit successfully adds 2 four bit numbers (5 Marks)

Show how the addition of extra gates allows the 4 bit adder to also operate as a subtractor. Implement using proteus (5 Marks)

Produce a graphical output that shows the subtractor subtracting 2 four bit numbers (5 Marks)

Task 3 :

Design and simulate a 4 – bit synchronous binary counter which counts from 0000 to1110

Modify the counter so that its count reaches 1011 and restarts 

Marks will be awarded as follows :

Theoretical design of 4 bit synchronous counter (5 Marks)

Schematic Design of 4 bit counter using Proteus (10 Marks)

Graphical output showing the counter counts from 0000 to 1111 and resets. (5 Marks)

Modified schematic to make the counter reset at 1011 (2 Marks)

Graphical output showing the modified counter counts from 0000 to 1011 and resets. (2 Marks)

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